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general description the max8737 dual high-power linear regulator con- trollers use external n-channel mosfets to generate two independent low-voltage supplies for notebook computers. the max8737 delivers low output voltages from 0.5v to 2.5v (?mv no-load accuracy). the exter- nal components allow scalable current design with loads up to 5a with excellent load regulation (1%). the regulator operates from a low input voltage, which also reduces the power dissipation in the external n-channel mosfet. the controller powers the external mosfet gate driver from the standard 5v system supply. the max8737 includes current and thermal limits to prevent damage to the linear regulator. the max8737 uses an external resistive divider to fold back the cur- rent limit, reducing the overall power dissipation. the max8737 uses an external resistive-divider in series with the current-sense input (cs_), providing foldback current-limit protection, and effectively reducing the short-circuit power dissipation. an output undervoltage timeout is available for low-cost applications that omit the current-sense resistor. the output undervoltage (uvp) timing depends on the mag- nitude of the voltage at v out . the uvp detects and shuts down the ldo if the output voltage drops out of regulation. the controller uses an adjustable reference input (refin_) to set the nominal output voltage (v out_ ), which minimizes the cost and makes the sta- bility independent of the output voltage. each linear regulator features an adjustable soft-start function, and generates a delayed power-good (pgood) signal that signals when the linear regulator is in regulation. the max8737 is a low-cost solution requiring few external components and is available in a small, 4mm x 4mm, 16-pin thin qfn package. applications notebook and desktop computers point-of-load regulators v mch and v ccp cpu supplies low-voltage bias supplies servers features ? low-cost dual linear regulators ? output voltage accuracy ?mv ? independent 0.5v to 2.5v reference inputs ? foldback current-limit protection ? output undervoltage-lockout protection ? thermal limit (internal sensor) ? 1.0v to 5.5v input supply voltage (external fet drain) ? 5v bias supply voltage ? independent power-good open-drain outputs ? independent enable inputs ? soft-shutdown output discharge ? low supply current (0.5ma) ? 5? (max) shutdown supply current max8737 dual, low-voltage linear regulator controllers with external mosfets ________________________________________________________________ maxim integrated products 1 16 1234 12 11 10 9 15 14 13 5 6 7 8 drv1 gnd n.c. drv2 n.c. cs2 out2 refin2 cs1 out1 refin1 pgood2 pgood1 en2 en1 v cc top view max8737 4mm x 4mm tqfn pin configuration 19-3705; rev 0; 5/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part temp range pin-package MAX8737ETE -40? to +85? 16 thin qfn-ep* 4mm x 4mm MAX8737ETE+ -40? to +85? 16 thin qfn-ep* 4mm x 4mm * ep = exposed pad. + denotes lead-free packaging.
max8737 dual, low-voltage linear regulator controllers with external mosfets 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ..............................................................-0.3v to +6v out1, out2 to gnd................................................-0.3v to +6v refin1, refin2, pgood1, pgood2, en1, en2 to gnd..........................................................-0.3v to +6v drv1, drv2, cs1, cs2 to gnd.................-0.3v to (v cc + 0.3v) continuous power dissipation (t a = +70?) 16-pin 4mm x 4mm thin qfn (derated 25mw/? above +70?).............................................................2000mw operating temperature range MAX8737ETE ...................................................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v cc = 5v, en_ = cs_ = v cc , v refin = 1.0v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units supply voltage range v cc 4.75 5.50 v v cc undervoltage lockout threshold rising edge, 200mv hysteresis (typ) 4.1 4.35 4.6 v v cc quiescent supply current i cc en1 = en2 = v cc 0.5 1 ma v cc shutdown supply current en1 = en2 = gnd 0.1 5 a refin to out offset voltage v out _-5+5mv out_ input bias current i out _-1+1a drivers output high; v out _ = v refin _ - 25mv, i load = 1ma v cc - 0.3 v cc - 0.05 drv_ output voltage swing (note 1) output low; v out _ = v refin _ + 25mv, i load = 1ma 0.03 0.3 v drv_ maximum sourcing current v out _ = v refin _ - 25mv; v drv = 3v 6 14 ma drv_ maximum sinking current v out _ = v refin _ + 25mv; v drv = 3v 6 14 ma out_ to drv_ transconductance (large signal) g mdrv 0.8 s drv_ power-supply rejection ratio 10hz < f < 10khz, i drv = 1ma, c drv = 10nf -80 db drv_ soft-start charging current i soft 40 170 400 ? reference input refin_ voltage range v refin _ v cc = 4.75v to 5.5v 0.5 2.5 v refin_ input bias current i refin _v refin _ = 0 to 2.5v -100 -10 +100 na fault protection thermal shutdown threshold t shdn hysteresis = 20? +125 ? t a = 0? to +85? 7 10 13 current-limit threshold v ilim v cs _ - v out _ t a = +85? 7.5 10 12.5 mv cs_ input current -1 +1 ? linear regulator uvp threshold (slow) uvp ( slow ) with respect to v refin ; cs_ = v cc 72 80 88 %
max8737 dual, low-voltage linear regulator controllers with external mosfets _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = 5v, en_ = cs_ = v cc , v refin = 1.0v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units linear regulator uvp threshold (fast) uvp ( fast ) with respect to v refin ; cs_ = v cc 54 60 66 % slow short-circuit timer duration t uvp ( slow ) with respect to v refin ; cs_ = v cc 75 ? fast short-circuit timer duration t uvp ( fast ) with respect to v refin ; cs_ = v cc 5s discharge-mode on-resistance out_ pin r out 10 ? inputs and outputs en_ input low level 0.6 v en_ input high level rising edge, 200mv (typ) hysteresis 1.6 v enable leakage current -1 +1 ? power-good trip threshold (lower) with respect to error comparator threshold, hysteresis = 4% (falling edge) -15 -12 -9 % power-good startup delay 2ms power-good propagation delay t pgood out_ forced 2% beyond pgood_ trip threshold 1s power-good output low voltage i sink = 4ma 0.3 v power good leakage current i goo v out _ = 1.0v (pgood_ high impedance), 1a electrical characteristics (v cc = 5v, en_ = cs_ = v cc , v refin = 1.0v, t a = -40? to +85? , unless otherwise noted.) (note 2) parameter symbol conditions min typ max units supply voltage range v cc 4.75 5.50 v v cc undervoltage lockout threshold rising edge 200mv hysteresis (typ) 4.1 4.6 v v cc quiescent supply current i cc en1 = en2 = v cc 1.5 ma v cc shutdown supply current en1 = en2 = gnd 5 a refin to out offset voltage v out _-7+7mv drivers output high; v out _ = v refin _ - 25mv; i load = 1ma v cc - 0.3 drv_ output voltage swing (note 1) output low; v out _ = v refin _ + 25mv: i load = 1ma 0.3 v drv_ maximum sourcing current v out _ = v refin _ - 25mv; v drv = 3v 3.5 ma drv_ maximum sinking current v out _ = v refin _ + 25mv; v drv = 3v 3.5 ma drv_ soft-start charging current i soft 40 400 ?
max8737 dual, low-voltage linear regulator controllers with external mosfets 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = 5v, en_ = cs_ = v cc , v refin = 1.0v, t a = -40? to +85? , unless otherwise noted.) (note 2) parameter symbol conditions min typ max units reference input refin_ voltage range v refin _ v cc = 4.75v to 5.5v 0.5 2.5 v fault protection current-limit threshold v ilim v cs _ - v out _ 6.5 13.5 mv linear regulator uvp threshold (slow) uvp ( slow ) with respect to v refin ; cs_ = v cc 72 88 % linear regulator uvp threshold (fast) uvp ( fast ) with respect to v refin ; cs_ = v cc 54 66 % inputs and outputs en_ input low level 0.6 v en_ input high level 1.6 v power-good trip threshold (lower) with respect to error comparator threshold, hysteresis = 4% (falling edge) -15 -9 % power-good output low voltage i sink = 4ma 0.3 v note 1: low threshold n-channel mosfet is required for 2.5v (?%) output. note 2: specifications to -40? are guaranteed by design, not production tested. t ypical operating characteristics (circuit of figure 1, t a = +25?, unless otherwise noted.) output-voltage deviation vs. load current max8737 toc01 load current (a) output-voltage deviation (mv) 1.5 1.0 0.5 -4 -3 -2 -1 0 1 2 3 4 5 -5 0 2.0 v out = 1.5v foldback current limit vs. output voltage max8737 toc02 output voltage (v) current limit (a) 1.0 0.5 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 0 0 1.5 1ms/div soft-start (en rising edge) 5v 3v c a d max8737 toc03 0 0 0 0 1.5v 5v a. en1, 5v/div b. drv1, 2v/div no load c. ldo1 output, 1v/div d. pgood1, 5v/div b
max8737 dual, low-voltage linear regulator controllers with external mosfets _______________________________________________________________________________________ 5 100 s/div soft-stop (en falling edge) 5v 3v c a d max8737 toc04 0 0 0 0 1.5v 5v a. en1, 5v/div b. drv1, 2v/div no load c. ldo1 output, 1v/div d. pgood1, 5v/div b 2ms/div soft-start (uvlo rising edge) 5v 3v c a d max8737 toc05 0 0 0 0 1.5v 5v a. 5v bias (v cc ), 5v/div b. drv1, 2v/div no load, en = v cc c. ldo1 output, 1v/div d. pgood1, 5v/div b 2ms/div soft-stop (uvlo falling edge) 5v 3v c a d max8737 toc06 0 0 0 0 1.5v 5v a. 5v bias (v cc ), 5v/div b. drv1, 2v/div no load, en = v cc c. ldo1 output, 1v/div d. pgood1, 5v/div b 10 s/div load transient (0.1a to 2.1a) 0 0.1a c a d max8737 toc07 1.50v 1.49v 2.1a 3.2v 2.8v a. control signal b. load current, 2a/div c. drv1, 500mv/div d. ldo1 output voltage, 10mv/div b 1.51v 10 s/div load transient (no load to 2a) 0 0 c a d max8737 toc08 1.50v 1.45v 2a 3.2v 2.7v a. control signal b. load current, 2a/div c. drv1, 1v/div d. ldo1 output voltage, 50mv/div b 1.7v 2 s/div load transient (no load to 2a) 0 0 c a d max8737 toc09 1.50v 1.45v 2a 3.2v 2.7v a. control signal b. load current, 2a/div c. drv1, 1v/div d. ldo1 output voltage, 50mv/div b t ypical operating characteristics (continued) (circuit of figure 1, t a = +25?, unless otherwise noted.)
max8737 dual, low-voltage linear regulator controllers with external mosfets 6 _______________________________________________________________________________________ drv transconductance distribution max8737 toc13 transconductance (s) sample percentage (%) 1.3 1.0 0.8 10 20 30 40 50 0 0.5 1.5 sample size = 150 out1 out2 output-voltage deviation vs. temperature max8737 toc14 temperature ( c) output-voltage deviation (mv) 60 35 10 -15 -2 -1 0 1 2 3 -3 -40 85 0. 1110 0.001 0.01 gain and phase (out1) 60 max8737 toc15 20 0 gain (db) phase ( ) 40 -20 180 0 -90 90 -180 frequency (mhz) 1.5v output, 1a load, c out = (1) 10 f 1206 16v ceramic 0. 1110 0.001 0.01 gain and phase (out2) 60 max8737 toc16 20 0 gain (db) phase ( ) 40 -20 180 0 -90 90 -180 frequency (mhz) 1.05v output, 2a load, c out = (1) 22 f 1206 6v ceramic t ypical operating characteristics (continued) (circuit of figure 1, t a = +25?, unless otherwise noted.) 2 s/div foldback current limit (short-circuit response) 10v c a d max8737 toc10 1.50v 5v 3v 20a 0 a. gate of fet load, 10v/div b. drv1, 1v/div c. mosfet current, 20a/div d. ld01 output voltage, 2v/div e. pgood1, 5v/div b 0 0 0 1.5v e output offset voltage distribution max8737 toc11 output offset voltage (mv) sample percentage (%) 3 0 -3 10 20 30 40 50 0 -5 5 sample size = 150 out1 out2 current-limit threshold distribution max8737 toc12 current limit (mv) sample percentage (%) 11.3 10.0 8.8 10 20 30 40 50 0 7.5 12.5 sample size = 150 out1 out2
max8737 dual, low-voltage linear regulator controllers with external mosfets _______________________________________________________________________________________ 7 max8737 dual, low-voltage linear regulator controllers with external mosfets pin description pin name function 1v cc analog and driver supply input. connect to the system supply voltage (+5.0v). bypass v cc to analog ground with a 1? or greater ceramic capacitor. 2 cs1 positive current-sense input for ldo1. to enable (foldback) current limit, connect cs1 to the positive terminal of the current-sense element as shown in figure 1. the max8737 driver reduces the gate voltage when the 10mv (typ) current-limit threshold is exceeded. when cs1 is connected to v cc , the max8737 disables the current-limit protection and enables the output undervoltage protection (see the uvp short-circuit protection section). 3 out1 outp ut feed b ack- s ense, n eg ati ve c ur r ent- s ense, and d i sc har g e inp ut for ld o 1. c o nnect d i r ectl y to the l i near r eg ul ator outp ut. w hen ld o1 i s d i sab l ed , ou t1 i s d i sc har g ed thr oug h an i nter nal 10 ? fe t to gn d . 4 refin1 external reference input for ldo1. refin1 sets the main output regulation voltage (v out1 = v refin1 ). 5 pgood2 open-drain power-good output for ldo2. pgood2 is low when the output voltage is more than 12% (typ) below the normal regulation point, during soft-start, and in shutdown. approximately 2ms (typ) after out2 reaches the regulation voltage (refin2), pgood2 becomes high impedance as long as the output remains in regulation. 6 pgood1 open-drain power-good output for ldo1. pgood1 is low when the output voltage is more than 12% (typ) below the normal regulation point, during soft-start, and in shutdown. approximately 2ms (typ) after out1 reaches the regulation voltage (refin1), pgood1 becomes high impedance as long as the output remains in regulation. 7 en2 enable input for ldo2. connect en2 to vcc for always on. when en2 is pulled low, the linear regulator shuts down and pulls the output to ground. 8 en1 enable input for ldo1. connect en1 to vcc for always on. when en1 is pulled low, the linear regulator shuts down and pulls the output to ground. 9 refin2 external reference input for the secondary regulator (ldo2). refin2 sets the main output regulation voltage (v out2 = v refin2 ). 10 out2 output sense, negative current-sense input, and discharge input for the secondary regulator (ldo2). connect directly to the linear regulator output. when the ldo2 is disabled, out2 is discharged through an internal 10 ? fet to gnd. 11 cs2 positive current-sense input for ldo2. to enable (foldback) current limit, connect cs2 to the positive terminal of the current-sense element as shown in figure 1. the max8737 driver reduces the gate voltage when the 10mv (typ) current-limit threshold is exceeded. when cs2 is connected to v cc , the max8737 disables the current-limit protection and enables the output undervoltage protection (see the uvp short-circuit protection section). 12, 14 n.c. not internally connected 13 drv2 external n-channel gate drive for ldo2 15 gnd ground. connect the thin qfn backside pad to gnd. 16 drv1 external n-channel gate drive for ldo1 ? p exposed pad. connect the thin qfn backside pad to gnd.
max8737 detailed description the max8737 is a dual, low-dropout, external n-chan- nel linear regulator controller for low-voltage notebook computer power supplies. the linear regulator provides a 0.5v to 2.5v (?mv no-load) output for powering the low-voltage supplies to desktop and notebook cpu chipsets (v ccp and v cc _ mch ). the regulator operates from low input voltage, which also reduces the power dissipation in the external n-channel mosfet. the con- troller powers the external mosfet gate driver from the standard 5v system supply. the controller features independent enable inputs (en_), pgood outputs (pgood_), input undervoltage lockout (uvlo), and output undervoltage protection (uvp). the controller uses an adjustable reference input (refin_) to set the nominal output voltage (v out ), which minimizes the cost and makes the stabili- ty independent of the output voltage. an output uvp timing depends on the magnitude of the voltage at v out . the uvp detects and shuts down the ldo if the output voltage drops below the nominal output voltage (v refin ). each linear regulator features an adjustable soft-start function, and generates a delayed pgood signal that signals when the linear regulator is in regula- tion. the max8737 uses an external resistor-divider in series with the current-sense input (cs_), providing foldback current-limit protection, and effectively reduc- ing the short-circuit power dissipation. the max8737 is available in a thin qfn package to reduce the thermal impedance, and improve the thermal coupling between the controller and the external mosfets. refin input the low-cost linear regulator uses an adjustable refer- ence input (refin_) to set the nominal output voltage, which minimizes cost and simplifies the stability?he stability calculation is independent of v out . the output voltage accuracy depends on the accuracy of the source generating the refin voltage. multiple accurate references are typically available elsewhere in the sys- tem (such as the switching regulator providing the low- voltage input supply). if lower output accuracy is acceptable, divide down and filter another regulated output voltage supply. to set output voltage, select r2 = 100k ? and select r1 using the following formula: soft-start when the ldo is activated, the respective drv_ is pulled up from gnd with a typical soft-start current of 170?. the soft-start current limits the output voltage slew rate and also limits the initial current spike through the external n-channel mosfet. the slew rate is also limited by the compensation capacitance used at the drv_ pin. the maximum drain current during startup is the ratio of c out to c comp , multiplied by the soft-start current i soft of 170? (typ). enable and power good the max8737 has independent enable control inputs (en1, en2). drive en1 high to enable output 1. drive en2 high to enable output 2. when en_ is driven low, the corresponding drv_ and pgood_ pins are pulled to gnd, and the output is discharged through a 10 ? switch. there are two independent pgood_ outputs indicating the supply status. pgood_ is pulled high 2ms after the controller is enabled (en_ is pulled high and v cc exceeds its uvlo threshold), and the output is in regu- lation. if either output is out of regulation, the respective pgood_ goes low immediately. the max8737 pulls pgood_ low if the output voltage drops below the lower trip threshold of -12% (typ) or when v cc is in uvlo or when en_ is pulled low. soft-stop the max8737 enables a soft-stop function that dis- charges the output through an internal 10 ? switch when en_ is driven low or v cc is in uvlo. the dis- charge time of the output depends on the output capacitance, output load, and the exact resistance of the internal discharge switch. to slow down the dis- charge rate, add resistance in series with the out_ pin. 5.0v bias supply (v cc ) the linear regulator operates with very low input volt- ages. v in may be as low as 1.2v, so a secondary 5v supply is required to provide sufficient bias to the gate drivers. locally decouple the v cc input with 1f or greater of ceramic capacitance. current limit the max8737 features a current limit that monitors the voltage across the current-sense resistor, which limits v cs _ - v out _ to 10mv (typ). however, in case of a short-circuit condition, the power dissipation across the external fet will be extremely high. to protect the external fet, the max8737 uses an external resistive divider (see figure 1) to fold back the current limit, reducing the overall power dissipation. the foldback r v v r ref refin 112 =? ? ? ? ? ? ? _ dual, low-voltage linear regulator controllers with external mosfets 8 _______________________________________________________________________________________
resistor network is calculated using the short-circuit current (i short ), the maximum load current (i max ), cur- rent-sense resistor (r cs ), the 10mv (?mv) current- limit threshold (v ilim ), and the external reference input (refin_). see figure 3: 1) pick the r cs requirement for maximum short-cir- cuit current: 2) select r1 = 10 ? and select r2 using the follow- ing formula: uvp short-circuit protection there are two levels of short-circuit uvp available in the controller. when the current-limit protection is not used (cs_= v cc ), the output undervoltage timeout protection is enabled, which protects the regulator against short circuits. output uvp timing depends on the magnitude of the output voltage drop. to clear the uvp fault latch, toggle the respective en_ input, or cycle v cc below its uvlo threshold. r vvr ir v refin ilim max cs ilim 2 1 = + ? () rvi cs ilim short = / max8737 dual, low-voltage linear regulator controllers with external mosfets _______________________________________________________________________________________ 9 r6b 100k ? power good 2 * a local 10 f ceramic capacitor will be sufficient for most applications. if the max8737 is powered from a high-impedance source, additional low-esr polymer capacitors are recommended on the input. n2 r3b 33 ? c2b 0.22 f c in2 10 f c sys2 * 100 f c out2 22 f 1.05v 3a (max) input 1.25v to 1.5v on off r2a 100k ? r1a 33.2k ? on off r6a 100k ? power good 1 c in1 10 f c sys1 * 100 f c out1 10 f 1.5v 2a (max) c1 1.0 f 5v bias supply input 1.8v to 2.5v r3a 27 ? c2a 0.1 f gnd refin1 en1 out1 drv1 pgood1 v cc pgood2 drv2 out2 en2 max8737 note: the system reference is typically generated by the step-down converter used to power the dual low-voltage linear regulators. r4b 10 ? r5b 150 ? r1b 90k ? r2b 100k ? system ref (2.0v) system ref (2.0v) r4a 10 ? r5a 340 ? n1 refin2 r cs2 20m ? r cs1 20m ? cs1 cs2 n1/n2: si 4922dy figure 1. typical operating circuit with current limit
max8737 dual, low-voltage linear regulator controllers with external mosfets 10 ______________________________________________________________________________________ en out 10 ? rdson current sense error amplifier refin r1 r2 en c1 r6 pgood the max8737 includes two ldos as shown above. ref gnd 88% 80% 60% control block delay logic ilim_en en q s r 75 s delay ilim_en cs drv 0.4v v cc max8737 c in r3 n1 r cs c out 4.7 f/a output c2 thermal shdn 5v bias supply input 1.0v to 5.5v off on power good logic supply figure 2. functional diagram
slow uvp if the output drops below 80% of the nominal output voltage (v refin ) for 75?, the max8737 shuts down the ldo and pulls the drv_ pin to ground. if the output voltage returns above 80% of the nominal output volt- age (v refin ) within the 75?, the controller ignores the load transient. fast uvp if the output voltage drops below 60% of the nominal output voltage (v refin ) for approximately 5?, the max8737 immediately shuts down and pulls the drv_ pin to ground. if the output voltage returns above 80% of the nominal output voltage (v refin ) within the 5?, the controller ignores the load transient. thermal protection the max8737 is available in a thin qfn package to reduce the thermal impedance, and improve the ther- mal coupling between the controller and the external mosfets. when the controller? junction temperature exceeds t j = +125? (max), a thermal sensor turns off the external pass transistor, allowing the system to cool. the thermal sensor turns the pass transistor back on once the controller? junction temperature drops by approximately 20?. design procedure input capacitor selection (c in ) typically, the max8737 is powered from the output of a step-down regulator, effectively providing a low-imped- ance source. a local 10? ceramic capacitor at v in and a 1.0? ceramic capacitor at v bias should be sufficient for most applications. if the linear regulator is connect- ed to a high-impedance input, low-esr polymer capac- itors are recommended on the input. output capacitor selection (c out ) to maintain stability and provide good transient response, the max8737 requires 4.7?/a (4.7? mini- mum) of low esr ceramic capacitor at the output. the regulator remains stable with capacitances higher than the minimum. when selecting the output capacitor to max8737 dual, low-voltage linear regulator controllers with external mosfets ______________________________________________________________________________________ 11 v out c out r cs c in input r3 c2 cs out drv max8737 max8737 v out c out r cs c in input r3 c2 cs out drv r1 r2 10mv r cs i max v out 10mv r cs i max v out simple current-limit protection foldback current-limit protection figure 3. current-limit protection
max8737 provide good transient response, the capacitor? esr should be minimized: ? v out = ? i out x esr where ? i out is the maximum peak-to-peak load current step, and ? v out is the transient output-voltage tolerance. regulator compensation the compensation network (r3_, c2_) is customizable and depends on load and mosfet characteristics: use of ceramic output capacitors with low r esr to ensure stability and minimize esr voltage drop at load step ? trength of the external n-channel mosfet (g m ), its forward transconductance (g fs ), and the gate-to- source capacitance (c gs ) the driver transconductance (g mdrv ) of the inte- grated circuit driver load current range (including the minimum load): i min to i max recommended procedure use the c gs ,g fs, i d from the chosen transistor data sheet and use the equation below to translate the mea- sured g fs to g m for normal operation: 1) determine the ldo transconductance using the mosfet? forward transconductance (g fs ), and the drain current (i d ) used to test the selected mosfet: 2) calculate the compensation resistor based on the output capacitor (c out ), the mosfet? gate-to- source capacitance (c gs = c iss - c rss ), and the minimum driver transconductance: 3) calculate the compensation capacitance using the minimum load current (i min ) and compensation resistor value calculated above: where v t = 25mv. example: the example below is used to demonstrate the stability calculation for the application circuit in figure 1. 1) choose v out = 1.05v and i max = 3a and the mini- mum load can be determined from the foldback cur- rent-limit resistance: 2) for the selected mosfet (si4922dy), c gs = 2000pf at 1.5v, and g fs = 30s at i d = 8.8a: 3) the output capacitor must be at least 4.7?/a. therefore the design must use a minimum 14.1? capacitor. the closest standard capacitor value is 22?. 4) based on the above operating conditions and com- ponent selection, the compensation resistor value should be: 5) finally, select the compensation capacitor value: external mosfet selection the max8737 uses an n-channel mosfet as the series pass transistor instead of a p-channel mosfet to reduce cost. the selected mosfet must have a gate threshold voltage (at the required max load) that meets the following criteria: where v cc is the controller bias voltage, and v gs_max is the maximum gate voltage required to yield the on- resistance (r ds_on ) specified by the manufacturer? data sheet. make sure that input-to-output voltage meets the condition below to avoid entering dropout, where output voltage starts to decrease and any ripple on the input also passes through to the output. r dson has a positive temperature coefficient (approximately vvv gs max cc out _ ? c mv f ma s f 2 225 22 6135 015 2 = = () . ? r f nf s s 3 22 217505 35 = = .. ? gs a a s m == 30 3 88 17 5 . . i v rr ma min out = + 12 6 c vc ig r t out min mdrv 2 2 3 2 = () r c cgx s out gs m 3 05 = . gg i i mfs max d = dual, low-voltage linear regulator controllers with external mosfets 12 ______________________________________________________________________________________
0.5%/?); therefore, the value of r dson at the highest operating junction temperature should be used: where v in_min is the minimum input voltage at the drain of the mosfet. mosfet power dissipation the maximum power dissipation of the max8737 depends on the thermal resistance of the external n- channel mosfet package, the board layout, the tem- perature difference between the die and ambient air, and the rate of airflow. the power dissipated in the mosfet is: p dis = i out (v in - v csp ) the maximum allowable power dissipation is deter- mined by the following formula: where t j(max) is the maximum junction temperature (+150?), t a is the ambient temperature, jc is the thermal resistance from the die junction to the package case, and ca is the thermal resistance from the case through the pc board, copper traces, and other materi- als to the surrounding air. standard 8-pin so mosfets are typically rated for 2w, while new power packages (powerpak, directfet, etc.) can achieve power dissipation ratings as high as 5w. for optimum power dissipation, use a large ground plane with good ther- mal contact to ground and use wide input and output traces. extra copper on the pc board increases ther- mal mass and reduces the thermal resistance of the board. see figure 4. pc board layout guidelines due to the high-current paths and tight output accuracy required by most applications, careful pc board layout is required. an evaluation kit (max8737evkit) is avail- able to speed design. i t is important to keep all traces as short as possible to minimize the high- current trace dimensions to reduce the effect of undesirable parasitic inductance. the mosfet dissi- pates a fair amount of heat due to the high currents involved, especially during large input-to-output voltage differences. to dissipate the heat generated by the mosfet, make power traces very wide with a large amount of copper area. an efficient way to achieve good power dissipation on a surface-mount package is to lay out copper areas directly under the mosfet package on multiple layers and connect the areas through vias. use a ground plane to minimize imped- ance and inductance. in addition to the usual high-power considerations, here are four tips to ensure high output accuracy: ensure that the feedback connection to c out is short and direct. place the reference input resistors next to the refin_ pin. place rc and cc next to the drv_ pin. ensure refin_ and drv_ traces are away from noisy sources to ensure tight accuracy. r tt dis max j max a jc ca () () = ? + ? vv ir r in min out max max dson max cs __ _ () ? + max8737 dual, low-voltage linear regulator controllers with external mosfets ______________________________________________________________________________________ 13 powerpak is a registered trademark of vishay siliconix. directfet is a trademark of international rectifier corp.
max8737 dual, low-voltage linear regulator controllers with external mosfets 14 ______________________________________________________________________________________ r6b 100k ? power good 2 n2 r3b 33 ? c2b 0.22 f c in2 10 f c sys2 * 100 f c out2 22 f 1.05v 3a (max) input 1.25v to 1.5v on off r9 100k ? r8 42.2k ? r7 47.5k ? on off r6a 100k ? power good 1 c in1 10 f c sys1 * 100 f c out1 10 f 1.5v 2a (max) c1 1.0 f 5v bias supply input 1.8v to 2.5v r3a 27 ? c2a 0.1 f gnd refin2 refin1 en1 out1 drv1 pgood1 cs1 v cc cs2 pgood2 drv2 out2 en2 max8737 note: the system reference is typically generated by the step-down converter used to power the dual low-voltage linear regulators. system ref (2.0v) n1 n1/n2: si 4922dy *a local 10 f ceramic capacitor is sufficient for most applications. if the max8737 is powered from a high-impedance source, additional low-esr polymer capacitors are recommended on the input. figure 4. typical operating circuit with output undervoltage protection chip information transistor count: 1562 process: bicmos
max8737 dual, low-voltage linear regulator controllers with external mosfets maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 d 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package outline, 21-0139 2 2 d 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm

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